1. Field of the Invention
The present invention relates generally to the design and fabrication of packages for semiconductor devices. More particularly, this invention relates to a semiconductor package having a metal ring connected to a rigid metal substrate.
2. Description of Related Art
Recent advances in the design and fabrication of silicon devices provide for gate delays as low as a fraction of a nanosecond, producing operating frequencies in the gigahertz range. The packaging of such devices, however, promises to be problematic. Although packaging is only a part of the overall chip to chip communication system, signal degradation at the package level frequently accounts for a disproportionate share of the degradation in the overall system.
Signal degradation can arise from a variety of factors, including (1) variations in signal line impedance, causing signal reflections which are a major sources of noise; (2) resistive losses in the internal package transmission lines, causing signal attenuation; (3) capacitive coupling between adjacent signal transmission lines, causing crosstalk which is another major source of noise; (4) inductive coupling, particularly in the power and ground connections, causing wave form degradation and crosstalk between the various signals; (5) switching noise, an inductive voltage spike that occurs on a conductive path as the result of a rapid current switching in the conductive path or nearby paths; and (6) crosstalk, the undesirable appearance of a voltage spike in a conductive path as a result of mutual capacitance and inductance between the conductive path and other nearby conductive paths.
Previously, ground and power planes have been used in integrated circuit packages in an attempt to provide uniform ground and power supplies to the integrated circuit and to reduce electrical noise. Such power and ground planes have been disclosed, for example, in U.S. Pat. No. 5,457,340 to Templeton, Jr. et al. issued Oct. 10, 1995.
The Templeton patent discloses a leadframe having a plurality of electrically conductive leads and an electrically conductive ring or ring segments formed on the leadframe around the circumference of the die attach pad between the die attach pad and leads. The power and ground planes in Templeton are formed as part of the leadframe.
Another type of ground plane is disclosed in U.S. Pat. No. 5,438,478 to Kondo et al. issued Aug. 1, 1995. The Kondo patent discloses a metal heat spreader attached to a semiconductor device partially enclosed in a molding resin. The metallic heat spreader may be connected to either power or ground. The Kondo patent discloses that the heat spreader covers the chip and only a small portion of the inner leadframe.
Still another type of ground plane is disclosed in U.S. Pat. No. 4,839,717 to Phy et al. issued Jun. 13, 1989. The Phy patent discloses a ceramic package having a ground ring surrounding the chip, but not over it, and covering the inner leadframe. The Phy patent also discloses a ground ring on the periphery of the chip which is connected to the ground ring surrounding the chip on the ceramic package.
The above-described ground planes suffer from the disadvantage that they fail to provide reduced noise capability on those portions of the leadframe not covered by the ground ring. Therefore, a package design is needed which substantially reduces noise and cross-talk in the circuits for not just the leads near the chip, but the areas surrounding the chip as well.
Furthermore, semiconductor packages are needed which minimize some or all of the degradative factors listed above. In particular, it would be desirable to provide a package which minimizes variations in signal transmission line impedance, minimizes resistive losses in the signal transmission lines, reduces capacitive coupling between adjacent signal transmission lines and reduces inductive coupling in the power and/or ground connections.